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19-2715; Rev 1; 2/05
16-Bit DACs with 16-Channel Sample-and-Hold Outputs
General Description
The MAX5621/MAX5622/MAX5623 are 16-bit digital-toanalog converters (DACs) with 16 sample-and-hold (SHA) outputs for applications where a high number of programmable voltages are required. These devices include a clock oscillator and a sequencer that updates the DAC with codes from an internal SRAM. No external components are required to set offset and gain. The MAX5621/MAX5622/MAX5623 feature a -4.5V to +9.2V output voltage range. Other features include a 200V/step resolution, with output linearity error, typically 0.005% of full-scale range (FSR). The 100kHz refresh rate updates each SHA every 320s, resulting in negligible output droop. Remote ground sensing allows the outputs to be referenced to the local ground of a separate device. These devices are controlled through a 20MHz SPITM/QSPITM/MICROWIRETM-compatible 3-wire serial interface. Immediate update mode allows any channel's output to be updated within 20s. Burst mode allows multiple values to be loaded into memory in a single, high-speed data burst. All channels are updated within 330s after data has been loaded. Each device features an output clamp and output resistors for filtering. The MAX5621 features a 50 output impedance and is capable of driving up to 250pF of output capacitance. The MAX5622 features a 500 output impedance and is capable of driving up to 10nF of output capacitance. The MAX5623 features a 1k output impedance and is capable of driving up to 10nF of output capacitance. The MAX5621/MAX5622/MAX5623 are available in 64-pin TQFP (10mm x 10mm) and 68-pin thin QFN (10mm x 10mm) packages.
Features
Integrated 16-Bit DAC and 16-Channel SHA with SRAM and Sequencer 16 Voltage Outputs 0.005% Output Linearity 200V Output Resolution Flexible Output Voltage Range Remote Ground Sensing Fast Sequential Loading: 1.3s per Register Burst and Immediate Mode Addressing No External Components Required for Setting Gain and Offset Integrated Output Clamp Diodes Three Output Impedance Options MAX5621 (50), MAX5622 (500), and MAX5623 (1k)
MAX5621/MAX5622/MAX5623
Ordering Information
PART MAX5621UCB MAX5621UTK MAX5622UCB MAX5622UTK MAX5623UCB MAX5623UTK TEMP RANGE* 0oC to +85oC 0oC to +85oC 0 C to +85 C 0oC to +85oC 0oC to +85oC 0 C to +85 C
o o o o
PIN-PACKAGE 64 TQFP 68 Thin QFN-EP** 64 TQFP 68 Thin QFN-EP** 64 TQFP 68 Thin QFN-EP**
*For other temperature ranges, contact factory. **EP = Exposed pad.
Pin Configurations
63 OUT15 61 OUT14 59 OUT13 56 OUT12 68 N.C. 66 VREF 64 N.C. 62 N.C. 60 N.C. 57 N.C. 55 N.C. 67 CH 53 N.C. 33
TOP VIEW
54 OUT11
65 AGND
58 AGND
________________________Applications
MEMS Mirror Servo Control Industrial Process Control Automatic Test Equipment Instrumentation
N.C. 1 N.C. 2 GS 3 VLDAC 4 RST CS DIN SCLK VLOGIC IMMED ECLK CLKSEL
5 6 7 8 9 10 11 12
52 CL 51 N.C. 50 VDD 49 CH 48 VSS 47 OUT10 46 N.C. 45 OUT9 44 N.C. 43 OUT8 42 AGND 41 VDD 40 N.C. 39 OUT7 38 N.C. 37 OUT6 36 N.C. 35 CL 34
MAX5621 MAX5622 MAX5623
DGND 13 VLSHA 14 AGND 15 VSS 16 N.C. 17 CL 19 OUT0 20 N.C. 21 OUT1 22 N.C. 23 OUT2 24 N.C. 25 AGND 26 OUT3 27 N.C. 28 OUT4 29 N.C. 30
31
VDD 18
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor, Corp.
THIN QFN
Pin Configurations continued at end of data sheet. 1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
OUT5 CH VSS N.C.
32
16-Bit DACs with 16-Channel Sample-and-Hold Outputs MAX5621/MAX5622/MAX5623
ABSOLUTE MAXIMUM RATINGS
VDD to AGND.......................................................-0.3V to +12.2V VSS to AGND .........................................................-6.0V to +0.3V VDD to VSS ...........................................................................+15V VLDAC, VLOGIC, VLSHA to AGND or DGND ..............-0.3V to +6V REF to AGND............................................................-0.3V to +6V GS to AGND................................................................VSS to VDD CL and CH to AGND...................................................VSS to VDD Logic Inputs to DGND ..............................................-0.3V to +6V DGND to AGND........................................................-0.3V to +2V Maximum Current into OUT_ ............................................10mA Maximum Current into Logic Inputs .................................20mA Continuous Power Dissipation (TA = +70C) 64-Pin TQFP (derate 13.3mW/C above +70C) ............1066mW 68-Pin Thin QFN (derate 28.6mW/C above +70C) ......2285mW Operating Temperature Range...............................0C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +10V, VSS = -4V, VLOGIC = VLDAC = VLSHA = +5V, VREF = +2.5V, AGND = DGND = VGS = 0V, RL 10M, CL = 50pF, CLKSEL = +5V, fECLK = 400kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC CHARACTERISTICS Resolution Output Range Offset Voltage Offset Voltage Tempco Gain Error Gain Tempco Integral Linearity Error Differential Linearity Error Maximum Output Drive Current DC Output Impedance INL DNL IOUT ROUT VOUT_ = -3.25V to +7.6V VOUT_ = -3.25V to +7.6V; monotonicity guaranteed to 14 bits Sinking and sourcing MAX5621 MAX5622 MAX5623 MAX5621 Maximum Capacitive Load DC Crosstalk Power-Supply Rejection Ratio PSRR MAX5622 MAX5623 Internal oscillator enabled (Note 3) Internal oscillator enabled 2 35 350 700 50 500 1000 250 10 10 -90 -80 65 650 1300 pF nF dB dB (Note 2) 5 0.005 1 0.015 4 N VOUT_ (Note 1) Code = 4F2C hex 16 VSS + 0.75 15 50 1 VDD 2.4 200 Bits V mV V/C % ppm/C %FSR LSB mA SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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16-Bit DACs with 16-Channel Sample-and-Hold Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +10V, VSS = -4V, VLOGIC = VLDAC = VLSHA = +5V, VREF = +2.5V, AGND = DGND = VGS = 0V, RL 10M, CL = 50pF, CLKSEL = +5V, fECLK = 400kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DYNAMIC CHARACTERISTICS Sample-and-Hold Settling SCLK Feedthrough fSEQ Feedthrough Hold-Step Droop Rate Output Noise REFERENCE INPUT Input Resistance Reference Input Voltage GROUND-SENSE INPUT Input Voltage Range Input Bias Current GS Gain Input High Voltage Input Low Voltage Input Current TIMING CHARACTERISTICS (Figure 2) Sequencer Clock Frequency External Clock Frequency SCLK Frequency SCLK Pulse Width High SCLK Pulse Width Low CS Low to SCLK High Setup Time CS High to SCLK High Setup Time SCLK High to CS Low Hold Time fSEQ fECLK fSCLK tCH tCL tCSSO tCSS1 tCSH0 15 15 15 15 10 Internal oscillator (Note 7) 80 100 120 480 20 kHz kHz MHz ns ns ns ns ns VIH VIL VGS IGS -0.5V VGS +0.5V (Note 6) -0.5 -60 0.998 2.0 0.8 1 1 +0.5 0 1.002 V A V/V V V A VREF 7 2.5 k V VOUT_ = 0V (Note 5), TA = +25C (Note 4) 0.5 0.5 0.25 1 250 1 40 0.08 % nV-s nV-s mV mV/s VRMS SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5621/MAX5622/MAX5623
DIGITAL INTERFACE DC CHARACTERISTICS
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3
16-Bit DACs with 16-Channel Sample-and-Hold Outputs MAX5621/MAX5622/MAX5623
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +10V, VSS = -4V, VLOGIC = VLDAC = VLSHA = +5V, VREF = +2.5V, AGND = DGND = VGS = 0V, RL 10M, CL = 50pF, CLKSEL = +5V, fECLK = 400kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SCLK High to CS High Hold Time DIN to SCLK High Setup Time DIN to SCLK High Hold Time RST to CS Low POWER SUPPLIES Positive Supply Voltage Negative Supply Voltage Supply Difference Logic Supply Voltage Positive Supply Current Negative Supply Current Logic Supply Current VLOGIC, VLDAC, VLSHA IDD ISS ILOGIC (Note 10) fSCLK = 20MHz (Note 11) VDD VSS (Note 9) (Note 9) VDD - VSS (Note 9) 4.75 5 32 32 1 2 8.55 -5.25 10 -4 11.60 -2.75 14.5 5.25 42 40 1.5 3 V V V V mA mA mA SYMBOL tCSH1 tDS tDH (Note 8) CONDITIONS MIN 0 15 0 500 TYP MAX UNITS ns ns ns s
Note 1: The nominal zero-scale (code = 0) voltage is -4.0535V. The nominal full-scale (code = FFFF hex) voltage is +9.0535V. The output voltage is limited by the Output Range specification, restricting the usable range of DAC codes. The nominal zeroscale voltage can be achieved when VSS < -4.9V, and the nominal full-scale voltage can be achieved when VDD > +11.5V. Note 2: Gain is calculated from measurements: for voltages VDD = 10V and VSS = -4V at codes C000 hex and 4F2C hex for voltages VDD = 11.6V and VSS = -2.9V at codes FFFF hex and 252E hex for voltages VDD = 9.25V and VSS = -5.25V at codes D4F6 hex and 0 hex for voltages VDD = 8.55V and VSS = -2.75V at codes C74A hex and 281C hex Note 3: Steady-state change in any output with an 8V change in an adjacent output. Note 4: Settling during the first update for an 8V step. The output settles to within the linearity specification on subsequent updates. Tested with an external sequencer clock frequency of 480kHz. Note 5: External clock mode with the external clock not toggling. Note 6: The output voltage is the sum of the DAC output and the voltage at GS. GS gain is measured at 4F2C hex. Note 7: The sequencer runs at fSEQ = fECLK/4. Maximum speed is limited by settling of the DAC and SHAs. Minimum speed is limited by acceptable droop and update time after a Burst Mode Update. Note 8: VDD rise to CS low = 500s maximum. Note 9: Guaranteed by gain-error test. Note 10: The serial interface is inactive. VIH = VLOGIC, VIL = 0V. Note 11: The serial interface is active. VIH = VLOGIC, VIL = 0V.
4
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16-Bit DACs with 16-Channel Sample-and-Hold Outputs
Typical Operating Characteristics
(VDD = +10V, VSS = -4V, VREF = +2.5V, VGS = 0V, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY VS. TEMPERATURE
MAX5621 toc02 MAX5621 toc03
MAX5621/MAX5622/MAX5623
INTEGRAL NONLINEARITY vs. CODE
MAX5621 toc01
DIFFERENTIAL NONLINEARITY vs. CODE
1.4 DIFFERENTIAL NONLINEARITY (LSB) 1.0 0.6 0.2 -0.2 -0.6 -1.0 -1.4 0.010
0.007 0.005 INTEGRAL NONLINEARITY (%) 0.003 0.001 -0.001 -0.003 -0.005 -0.007 4018 11769 19520 27271 35021 42723 58268 INPUT CODE
INTEGRAL NONLINEARITY (%)
0.008
0.006
0.004
0.002
4018 11769 19520 27271 35021 42723 58268 INPUT CODE
0 -40 -15 10 35 60 85 TEMPERATURE (C)
DIFFERENTIAL NONLINEARITY VS. TEMPERATURE
MAX5621 toc04
OFFSET VOLTAGE
VS. TEMPERATURE
MAX5621 toc05
DROOP RATE vs. TEMPERATURE
CODE = 4F2C hex EXTERNAL CLOCK MODE NO CLOCK APPLIED
MAX5621 toc06
1.0 DIFFERENTIAL NONLINEARITY (LSB)
-10 VDD = +8.55V VSS = -4V CODE = 4F2C hex
100 10 DROOP RATE (mV/s) 1 0.100 0.010 0.001 0.0001
0.9
-12 OFFSET VOLTAGE (mV)
0.8
-14
0.7
-16
0.6
-18
0.5 -40 -15 10 35 60 85 TEMPERATURE (C)
-20 -40 -15 10 35 60 85 TEMPERATURE (C)
-40
-15
10
35
60
85
TEMPERATURE (C)
GAIN ERROR VS. TEMPERATURE
MAX5621 toc07
POSITIVE SUPPLY PSRR VS. FREQUENCY
MAX5621 toc08
NEGATIVE SUPPLY PSRR VS. FREQUENCY
-80 -70 -60 PSRR (dB) -50 -40 -30 -20 -10 0 0.001 0.01 0.1 1 10 100
MAX5621 toc09
0.05
-90 -80 -70 -60 PSRR (dB)
-90
0.04 GAIN ERROR (%)
0.03
-50 -40 -30
0.02
0.01 CODE = C168 hex OFFSET CODE = 4F2C hex 0 -40 -15 10 35 60 85 TEMPERATURE (C)
-20 -10 0 0.01 0.1 1 FREQUENCY (kHz) 10 100
FREQUENCY (kHz)
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5
16-Bit DACs with 16-Channel Sample-and-Hold Outputs MAX5621/MAX5622/MAX5623
Typical Operating Characteristics (continued)
(VDD = +10V, VSS = -4V, VREF = +2.5V, VGS = 0V, TA = +25C, unless otherwise noted.)
LOGIC SUPPLY CURRENT vs. LOGIC SUPPLY VOLTAGE
MAX5621 toc10
LOGIC SUPPLY CURRENT
VS. LOGIC INPUT HIGH VOLTAGE
MAX5621 toc11
SUPPLY CURRENT vs. TEMPERATURE
34 SUPPLY CURRENT (mA) 32 30 28 26 24 ISS
MAX5621 toc12
900 LOGIC SUPPLY CURRENT (A)
1200 LOGIC SUPPLY CURRENT (A) 1000 800 600 400 200
36 IDD
800
700
600
500 INTERFACE INACTIVE 400 4.75 5.00 5.25 5.50 LOGIC SUPPLY VOLTAGE (V)
22 fSCLK = 20MHz INTERFACE INACTIVE 20 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -40 -15 10 35 60 85 LOGIC INPUT HIGH VOLTAGE (V) TEMPERATURE (C)
0
POSITIVE SETTLING TIME (8V STEP)
MAX5621 toc13
NEGATIVE SETTLING TIME (8V STEP)
MAX5621 toc14
POSITIVE SETTLING TIME (100mV STEP)
MAX5621 toc15
3.5V ECLK 0V ECLK
3.5V ECLK 0V
3.5V
0V
VOUT_ 5V/div VOUT_ 5V/div VOUT_ 50mV/div AC-COUPLED
1s/div
1s/div
1s/div
NEGATIVE SETTLING TIME (100mV STEP)
MAX5621 toc16
OUTPUT NOISE
MAX5621 toc17
3.5V ECLK 0V OUT_ 1mV/div 50mV/div AC-COUPLED
VOUT_
1s/div
250s/div
6
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16-Bit DACs with 16-Channel Sample-and-Hold Outputs
Pin Description
PIN TQFP 1, 2, 20, 22, 24, 27, 29, 34, 36, 38, 42, 44, 50, 52, 54, 57, 59, 61 3 4 5 6 7 8 9 10 11 12 13 14 15, 25, 40, 55, 62 16, 32, 46 17, 39, 48 18, 33, 49 19 21 23 26 28 30 35 37 41 43 45 31, 47, 64 51 53 56 58 60 63 THIN QFN 1, 2, 17, 21, 23, 25, 28, 30, 34, 36, 38, 40, 44, 46, 51, 53, 55, 57, 60, 62, 64, 68 3 4 5 6 7 8 9 10 11 12 13 14 15, 26, 42, 58, 65 16, 33, 48 18, 41, 50 19, 35, 52 20 22 24 27 29 31 37 39 43 45 47 32, 49, 67 54 56 59 61 63 66 NAME FUNCTION
MAX5621/MAX5622/MAX5623
N.C. GS VLDAC RST CS DIN SCLK VLOGIC IMMED ECLK CLKSEL DGND VLSHA AGND VSS VDD CL OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 CH OUT11 OUT12 OUT13 OUT14 OUT15 REF
No Connection. Not internally connected. Ground-Sensing Input +5V DAC Power Supply Reset Input Chip-Select Input Serial Data Input Serial Clock Input +5V Logic Power Supply Immediate Update Mode External Sequencer Clock Input Clock-Select Input Digital Ground +5V Sample-and-Hold Power Supply Analog Ground Negative Power Supply Positive Power Supply Output Clamp Low Voltage Output 0 Output 1 Output 2 Output 3 Output 4 Output 5 Output 6 Output 7 Output 8 Output 9 Output 10 Output Clamp High Voltage Output 11 Output 12 Output 13 Output 14 Output 15 Reference Voltage Input
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7
16-Bit DACs with 16-Channel Sample-and-Hold Outputs MAX5621/MAX5622/MAX5623
CH ECLK CLKSEL CLOCK R E G I S T E R SAMPLEAND-HOLD ARRAY OUT0
SAMPLE
DATA READY SEQUENCER
OUT15 CL
READ ENABLE SEQUENTIAL ADDRESS 2:1 M U X
16 x 16 SRAM
R E G I S T E R
16-BIT DAC
GAIN AND OFFSET CORRECTION
GS
REF
CS SCLK DIN IMMED RST SERIAL INTERFACE
LAST ADDRESS ADDR SELECT
WRITE ENABLE D[15:0]
MAX5621 MAX5622 MAX5623
Figure 1. Functional Diagram
tCSH1 CS tCSHO SCLK tDH tDS DIN B23 B22 B0
tCSSO
tCH
tCL
tCSS1
Figure 2. Serial Interface Timing Diagram
8
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16-Bit DACs with 16-Channel Sample-and-Hold Outputs
Detailed Description
Digital-to-Analog Converter
The MAX5621/MAX5622/MAX5623 16-bit digital-to-analog converters (DACs) are composed of two matched sections. The four MSBs are derived through 15 identical matched resistors and the lower 12 bits are derived through a 12-bit inverted R-2R ladder.
MAX5621/MAX5622/MAX5623
(VSS
+ 0.75V ) VOUT _ (VDD - 2.4V )
The device has a fixed theoretical output range determined by the reference voltage, gain, and midscale offset. The output voltage for a given input code is calculated with the following: code VOUT = x VREF x 5.2428 65535
Sample-and-Hold Amplifiers
The MAX5621/MAX5622/MAX5623 contain 16 buffered sample/hold circuits with internal hold capacitors. Internal hold capacitors minimize leakage current, dielectric absorption, feedthrough, and required board space. The MAX5621/MAX5622/MAX5623 provide a very low 1mV/s droop rate.
(1.6214 x VREF ) + VGS
where code is the decimal value of the DAC input code, VREF is the reference voltage, and VGS is the voltage at the ground-sense input. With a 2.5V reference, the nominal end points are -4.0535V and +9.0535V (Table 1). Note that these are "virtual" internal end-point voltages and cannot be reached with all combinations of negative and positive power-supply voltages. The nominal, usable DAC end-point codes for the selected power supplies can be calculated as: Lower end-point code = 32768 - ((2.5V - (VSS+0.75) / 200V) (result 0) Upper end-point code = 32768 + ((VDD - 2.4 - 2.5V) / 200V) (result 65535)
Output
The MAX5621/MAX5622/MAX5623 include output buffers on each channel. The device contains output resistors in series with the buffer output (Figure 3) for ease of output filtering and capacitive load driving stability. Output loads increase the analog supply current (IDD and ISS). Excessively loading the outputs drastically increases power dissipation. Do not exceed the maximum power dissipation specified in the Absolute Maximum Ratings. The maximum output voltage range depends on the analog supply voltages available and the output clamp voltages (see the Output Clamp section):
VREF GAIN AND OFFSET
CH 16-BIT DAC RO AV = 1 CHOLD ONE OF 16 SHA CHANNELS CL RL OUT_
DAC DATA
GS
Figure 3. Analog Block Diagram
Table 1. Code Table
DAC INPUT CODE MSB LSB 1111 1111 1111 1111 1100 0111 0100 1010 1000 0000 0000 0000 0100 1111 0010 1100 0010 1000 0001 1100 0000 0000 0000 0000 NOMINAL OUTPUT VOLTAGE (V) 9.0535 6.15 2.5 0 -2.0 -4.0535 Full-scale output Maximum output with VDD = 8.55V Midscale output VOUT_ = 0; all outputs default to this code after power-up Minimum output with VSS = -2.75V Zero-scale output VREF = +2.5V
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9
16-Bit DACs with 16-Channel Sample-and-Hold Outputs MAX5621/MAX5622/MAX5623
The resistive voltage-divider formed by the output resistor (RO) and the load impedance (RL), scales the output voltage. Determine VOUT_ as follows: Scaling Factor = VOUT _ = VCHOLD RL RL + RO x scaling factor
Table 2. Channel/Output Selection
A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT OUT0 selected OUT1 selected OUT2 selected OUT3 selected OUT4 selected OUT5 selected OUT6 selected OUT7 selected OUT8 selected OUT9 selected OUT10 selected OUT11 selected OUT12 selected OUT13 selected OUT14 selected OUT15 selected
Ground Sense
The MAX5621/MAX5622/MAX5623 include a groundsense input (GS), which allows the output voltages to be referenced to a remote ground. The voltage at GS is added to the output voltage with unity gain. Note that the resulting output voltage must be within the valid output voltage range set by the power supplies.
Output Clamp
The MAX5621/MAX5622/MAX5623 clamp the output between two externally applied voltages. Internal diodes at each channel restrict the output voltage to:
(VCH
+ 0.7V ) VOUT _ (VCL
-
0.7V )
The clamping diodes allow the MAX5621/MAX5622/ MAX5623 to drive devices with restricted input ranges. The diodes also allow the outputs to be clamped during power-up or fault conditions. To disable output clamping, connect CH to VDD and CL to VSS, setting the clamping voltages beyond the maximum output voltage range.
Serial Input Data Format and Control Codes
The 24-bit serial input format, shown in Figure 4, comprises 16 data bits (D15-D0), 4 address bits (A3-A0), 1 required zero bit after the address bits, 2 control bits (C1, C0), and a fill zero. The address code selects the output channel as shown in Table 2. The control code configures the device as follows: 1) If C1 = 1, immediate update mode is selected. If C1 = 0, burst mode is selected. 2) If C0 = 0, the internal sequencer clock is selected. If C0 = 1, the external sequencer clock is selected. This must be repeated with each data word to maintain external input. The operating modes can also be selected externally through CLKSEL and IMMED. In the case where the control bit in the serial word and the external signal conflict, the signal that is a logic 1 is dominant.
Serial Interface
The MAX5621/MAX5622/MAX5623 are controlled by an SPI/QSPI/MICROWIRE-compatible 3-wire interface. Serial data is clocked into the 24-bit shift register in an MSB-first format, with the 16-bit DAC data preceding the 4-bit SRAM address, required zero bit, 2-bit control, and a fill 0 (Figure 4). The input word is framed by CS. The first rising edge of SCLK after CS goes low clocks in the MSB of the input word. When each serial word is complete, the value is stored in the SRAM at the address indicated and the control bits are saved. Note that data can be corrupted if CS is not held low for an integer multiple of 24 bits. All of the digital inputs include Schmitt-trigger buffers to accept slow-transition interfaces. Their switching threshold is compatible with TTL and most CMOS logic levels.
DATA
ADDRESS D0 A3 A2 A1 A0 0
CONTROL C1 C0 0 LSB
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 MSB
Figure 4. Input Word Sequence 10 ______________________________________________________________________________________
16-Bit DACs with 16-Channel Sample-and-Hold Outputs MAX5621/MAX5622/MAX5623
Table 3. Update Mode
UPDATE MODE Immediate update mode Burst mode UPDATE TIME 2/fSEQ 33/fSEQ
SHA ARRAY UPDATE SEQUENCE 1 2 3 2/fSEQ 7 SKIP 12 7 8 9
CHANNEL 12 UPDATED CS LOAD ADDRESS 12 DIN 24-BIT WORD INTERRUPTED CHANNEL REFRESHED
Modes of Operation
The MAX5621/MAX5622/MAX5623 feature three modes of operation: * * * Sequence mode Immediate update mode Burst mode
Sequence Mode Sequence mode is the default operating mode. The internal sequencer continuously scrolls through the SRAM, updating each of the 16 SHAs. At each SRAM address location, the stored 16-bit DAC code is loaded to the DAC. Once settled, the DAC output is acquired by the corresponding SHA. Using the internal sequencer clock, the process typically takes 320s to update all 16 SHAs (20s per channel). Using an external sequencer clock the update process takes 128 clock cycles (eight clock cycles per channel). Immediate Update Mode Immediate update mode is used to change the contents of a single SRAM location, and update the corresponding SHA output. In immediate update mode, the selected output is updated before the sequencer resumes operation. Select immediate update mode by driving either IMMED or C1 high. The sequencer is interrupted when CS is taken low. The input word is then stored in the proper SRAM address. The DAC conversion and SHA sample in progress are completed transparent to the serial bus activity. The SRAM location of the addressed channel is then modified with the new data. The DAC and SHA are updated with the new voltage. The sequencer then resumes scrolling at the interrupted SRAM address. This operation can take up to two cycles of the sequencer clock. Up to one cycle is needed to allow the sequencer to complete the operation in progress before it is freed to update the new channel. An additional cycle is required to read the new data from memory, update the DAC, and strobe the sample-and-hold. The sequencer resumes scrolling from the location at which it was interrupted. Normal sequencing is suppressed while loading data, thus preventing other channels from
Figure 5. Immediate Update Mode Timing Example
being refreshed. Under conditions of extremely frequent immediate updates (i.e., 1000 successive updates), unacceptable droop can result. Figure 5 shows an example of an immediate update operation. In this example, data for channel 12 is loaded while channel 7 is being refreshed. The sequencer operation is interrupted, and no other channels are refreshed as long as CS is held low. Once CS returns high, and the remainder of an fSEQ period (if any) has expired, channel 12 is updated to the new data. Once channel 12 has been updated, the sequencer resumes normal operation at the interrupted channel 7. Burst Mode Burst mode allows multiple SRAM locations to be loaded at high speed. During burst mode, the output voltages are not updated until the data burst is complete and control returns to the sequencer. Select burst mode by driving both IMMED and C1 low. The sequencer is interrupted when CS is taken low. All or part of the memory can be loaded while CS is low. Each data word is loaded into its specified SRAM address. The DAC conversion and SHA sample in progress are completely transparent to the serial bus activity. When CS is taken high, the sequencer resumes scrolling at the interrupted SRAM address. New values are updated when their turn comes up in the sequence. After burst mode is used, it is recommended that at least one full sequencer loop (320s) is allowed to occur before the serial port is accessed again. This ensures that all outputs are updated before the sequencer is interrupted.
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11
16-Bit DACs with 16-Channel Sample-and-Hold Outputs MAX5621/MAX5622/MAX5623
2/fSEQ SHA ARRAY UPDATE SEQUENCE 6 7 SKIP SKIP SKIP 7 8 5 6 7
+5V
+10V
33/fSEQ TO UPDATE ALL CHANNELS CS LOAD MULTIPLE ADDRESSES DIN
0.1F
0.1F
VLOGIC VLDAC VLSHA +2.5V REF GS CS DIN
VDD OUT0
OUT1
Figure 6. Burst Mode Timing Example
SCLK IMMED
MAX5621 MAX5622 MAX5623
Figure 6 shows an example of a burst mode operation. As with the immediate update example, CS falls while channel 7 is being refreshed. Data for multiple channels is loaded, and no channels are refreshed as long as CS remains low. Once CS returns high, sequencing resumes with channel 7 and continues normal refresh operation. Thirty-three fSEQ cycles are required before all channels have been updated.
CLKSEL ECLK RST DGND AGND VSS OUT15 CL
0.1F -4V
External Sequencer Clock
An external clock can be used to control the sequencer, altering the output update rate. The sequencer runs at 1/4 the frequency of the supplied clock (ECLK). The external clock option is selected by driving either C0 or CLKSEL high. When CLKSEL is asserted, the internal clock oscillator is disabled. This feature allows synchronizing the sequencer to other system operations, or shutting down of the sequencer altogether during high-accuracy system measurements. The low 1mV/s droop of these devices ensures that no appreciable degradation of the output voltages occurs, even during extended periods of time when the sequencer is disabled.
Figure 7. Typical Operating Circuit
Applications Information
Power Supplies and Bypassing
Grounding and power-supply decoupling strongly influence device performance. Digital signals may couple through the reference input, power supplies, and ground connection. Proper grounding and layout can reduce digital feedthrough and crosstalk. At the device level, a 0.1F capacitor is required for the VDD, VSS, and VL_ pins. They should be placed as close to the pins as possible. More substantial decoupling at the board level is recommended and is dependent on the number of devices on the board (Figure 7). The MAX5621/MAX5622/MAX5623 have three separate +5V logic power supplies, VLDAC, VLOGIC, and VLSHA. VLDAC powers the 16-bit digital-to-analog converter, VLSHA powers the control logic of the SHA array, and VLOGIC powers the serial interface, sequencer, internal clock and SRAM. Additional filtering of V LDAC and VLSHA improves the overall performance of the device.
Power-On Reset
A power-on reset (POR) circuit sets all channels to 0V (code 4F2C hex) in sequence, requiring 320s. This prevents damage to downstream ICs due to arbitrary reference levels being presented following system power-up. This same function is available by driving RST low. During the reset operation, the sequencer is run by the internal clock, regardless of the state of CLKSEL. The reset process cannot be interrupted, and serial inputs are ignored until the entire reset process is complete.
12
______________________________________________________________________________________
16-Bit DACs with 16-Channel Sample-and-Hold Outputs
Pin Configurations (continued)
OUT15 OUT14 OUT13 OUT12 AGND AGND
Chip Information
TRANSISTOR COUNT: 16,229 PROCESS: BiCMOS
MAX5621/MAX5622/MAX5623
VREF
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
CH
TOP VIEW
OUT11
64
63 62 61 60 59 58
57 56 55 54 53 52 51 50 49
N.C. N.C. GS VLDAC RST CS DIN SCLK VLOGIC
CL
48 VDD 47 CH 46 VSS 45 OUT10 44 N.C. 43 OUT9 42 N.C. 41 OUT8 40 AGND 39 VDD 38 N.C. 37 OUT7 36 N.C. 35 OUT6 34 N.C. 33 CL
1 2 3 4 5 6 7 8 9
IMMED 10 ECLK 11 CLKSEL 12 DGND 13 VLSHA 14 AGND 15 VSS 16
MAX5621 MAX5622 MAX5623
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
OUT0
N.C.
VDD
N.C.
N.C.
N.C.
AGND
OUT1
OUT2
OUT3
OUT4
N.C.
TQFP
______________________________________________________________________________________
OUT5
VSS
CL
CH
13
16-Bit DACs with 16-Channel Sample-and-Hold Outputs MAX5621/MAX5622/MAX5623
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
64L TQFP.EPS
PACKAGE OUTLINE, 64L TQFP, 10x10x1.4mm
21-0083
B
1
2
PACKAGE OUTLINE, 64L TQFP, 10x10x1.4mm
21-0083
B
2
2
14
______________________________________________________________________________________
16-Bit DACs with 16-Channel Sample-and-Hold Outputs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 68L QFN THIN.EPS
MAX5621/MAX5622/MAX5623
PACKAGE OUTLINE 68L THIN QFN, 10x10x0.8mm
21-0142
C
1
2
______________________________________________________________________________________
15
16-Bit DACs with 16-Channel Sample-and-Hold Outputs MAX5621/MAX5622/MAX5623
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE 68L THIN QFN, 10x10x0.8mm
21-0142
C
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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